Trench isolation structures have received increasing use in integrated circuit device fabrication in order to improve operating characteristics of the integrated circuit device. However, as the need for smaller device size increases, isolation spaces must also be smaller in order to take advantage of the smaller device fabrication techniques. Conventional trench isolation structures are fabricated through LOCOS techniques. However, LOCOS isolation cannot be decreased to lithographic limits. Therefore, it is desirable to have a method of forming a trench isolation structure that can be scaled down to lithographic limits.